This simulator product makes source level debugging of applications possible in the Renesas integrated development environment, or the CS+, while the target system is not available on hand.
- RH850 core operates by architecture of each G3M/G3K/G3KH/G3MH/G4MH.
- Since the latency of access to the various types of memory and peripheral modules is not considered,the execution times (numbers of cycles) will be different from those for the actual device.
- Since the simulator/debugger runs on the host computer, the user can start debugging the program while the actual MCU is not available on hand. This will result in a reduced development period of the entire system.
- The functions outlined below are available, which permit program test and debug to be proceeded efficiently.
- Support each CPU in the RH850 Family.
- If an error occurs while the program under debug is running, the user can choose to continue ignoring the error or stop the program.
- Comprehensive break functions.
- Set and edit memory map.
- Display C and assembler source level coverages.
- The simulator/debugger runs under Windows, allowing breakpoints, memory map and trace to be set in dialog boxes.
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