High-end car information systems for 2015 onwards will demand high-definition displays, instrument cluster, multi-display output to the rear seat monitor, a user experience specialized for automotive, improved responsiveness, and cloud services that use big data. In addition, there will be strong demand for fast startup capability and rendering performance for high-quality design that matches the luxuriousness of the vehicle interior for these embedded devices, as well as field-of-view support for the driver to establish an even higher level of safety, such as a top view monitor that displays not only the back of but all around the vehicle. To respond to these requirements, continuing from the existing R-Car H1 SoC for high-end car information systems Renesas is releasing the first second-generation R-Car, the R-Car H2, which has vastly improved performance.

Features

  • Achieves the industry's highest performance for an SoC for car information systems of over 25000 DMIPS (double that of the R-Car H1 )
  • The first use of the G6400 high-performance graphics core with the latest PowerVR architecture for automotive
  • Equipped with the IMP-X4, which has four times the processing performance compared to the R-Car H1, to support OpenCV
  • More interfaces that are required for next-generation automotive applications (USB 3.0, Ethernet AVB, four-channel simultaneous input for a high-definition digital camera, three-channel video output, and more)
  • An ecosystem that includes partner solutions supports the fast development of prototypes and a large reduction in development costs (Operating systems such as QNX® Neutrino® RTO, Windows® Embedded Automotive, and Linux; board support packages; middleware; and development tools)

Applications

  • Car information systems

News & Additional Resources

Type Date
R-Car Consortium Page Jul 15, 2020
Automotive Software & Tools Page May 5, 2020

Specification

Item R-Car H2 Specifications
Product No. R8A7790x
Power Supply Voltage 3.3/1.8 V (IO), 1.5/1.35 V (DDR3), 1.0 V (Core)
CPU Core Arm®Cortex®-A15
Quad		 Arm®Cortex®-A7
Quad  (device option)		 SH-4A core
(device option)
Cache Memory L1 Instruction cache: 32 KB
L1 Operand cache: 32 KB
L2 Cache: 2 MB		 L1 Instruction cache: 32KB
L1 Operand cache: 32 KB
L2 cache: 512 KB		 Instruction cache: 32 KB
Operand cache: 32 KB
External Memory DDR3-SDRAM
Maximum operating frequency: 800 MHz
Data bus width: 32 bits × 2 ch (6.4 GB/s × 2)
Expansion Bus Flash ROM and SRAM
Data bus width: 8 or 16 bits
PCI Express2.0 (1 lane)
Graphics PowerVR Series 6 G6400 (3D)
Renesas graphics processor (2D）
Video Display Out × 3 ch ( 2 ch: LVDS, 1 ch: RGB888)
Video Input × 4 ch
Video codec module (H.264/AVC、MPEG-4、VC-1)
IP conversion module
JPEG accelerator
TS Interface × 2 ch
Video image processing (color conversion, image expansion, reduction, filter processing)
Distortion compensation module (image renderer) × 4 ch
High performance Real-time Image recognition processor (IMP-X4) (device option)
Audio Audio DSP
Sampling rate converter × 10 ch
Serial sound interface × 10 ch
MOST DTCP
Storage Interfaces USB 3.0 Host interface × 1 port (wPHY)
SD Host interface × 4 ch (SDXC, UHS-I)
SD Host interface × 4 ch (SDXC, UHS-I)
Multimedia card interface × 2 ch
Serial ATA interface × 2 ch
In Car Network and
Automotive Peripherals		 Media local bus (MLB) Interface × 1 ch (6-pin / 3-pin interface selectable)
Controller Area Network (CAN) Interface × 2 ch
IEBus Interface
GPS baseband module (Galileo, GLONASS) (device option)
Ethernet controller AVB (IEEE802.1BA, 802.1AS, 802.1Qav and IEEE1722, GMII/MII, without PHY)
Security Crypto engine (AES, DES, Hash, RSA）
SecureRAM
Other Peripherals LBSC DMAC: 3 ch / SYS-DMAC: 30 ch / RT-DMAC: 3 ch /
Audio-DMAC: 26 ch / Audio(peripheral)-DMAC: 29 ch
32-bit timer × 12 ch
PWM timer × 7 ch
I2C bus interface × 8 ch
Serial communication interface (SCIF) × 10 ch
Quad serial peripheral interface (QSPI) × 1 ch (for boot)
Clock-synchronized serial interface (MSIOF) × 4 ch (SPI/IIS)
Ethernet controller (IEEE802.3u, RMII, without PHY)
Interrupt controller (INTC)
Clock generator (CPG) with built-in PLL
On chip debugger interface
Low Power Mode Dynamic Power Shutdown (CPU core, 3D, IMP)
AVS and DVFS function
DDR-SDRAM power supply backup mode
Package 831-pin Flip Chip BGA (27 mm × 27 mm)
Development
Environment		 ICE for Arm CPU available from different vendors
Evaluation Board A user system development reference platform offering the following features is also available, enabling the users to carry out efficient system development.
(1) Includes car information system-oriented peripheral circuits, providing users with an actual device verification environment.
(2) Can be used as a software development tool for application software, etc.
(3) Allows easy implementation of custom user functions.
Software Platform Support OS: QNX®Neutrino®RTOS、Windows®Embedded Automotive、Linux
Wide variety of H.264, MPEG-4 and VC-1 for video compliant with OpenMAX IL I/F in addition to BSPs compliant with OSs standard API are available to realize complete system concept.

(Remarks)
DMIPS: Dhrystone Million Per Second
Open CV: Open Source Computer Vision Library
Arm, Cortex is a registered trademark of Arm Limited. NEON is a trademark of Arm Limited.
PowerVR, SGX is a trademark or a registered trademark of Imagination Technologies Ltd. (UK).v
CAN (Controller Area Network): An automotive network specification developed by Robert Bosch GmbH of Germany.
IEBus™ is a trademark of Renesas Electronics Corporation.
QNX and Neutrino are trademarks of QNX Software Systems GmbH & Co. KG, registered in certain jurisdictions, and are used under license by QNX Software Systems Co.
Windows is a registered trademark or trademark of Microsoft Corporation in the United States and/or other countries.
Linux is a registered trademark or trademark of Linus Torvalds in Japan and other countries.
Other product name and service name under release are the trademarks or registered trademarks that all belong to each owner.