The R-Car H3 delivers computing capabilities that exceed those of its predecessor the R-Car H2, enabling it to be used as the automotive computing platform for the autonomous-driving era. The R-Car H3 is compliant with the ISO 26262 (ASIL-B) functionality safety standard for automotive, and has enhanced security functions and improved robustness. The R-Car H3 is a solution that can be applied to a wide range of in-vehicle infotainment systems as well as driving safety support systems.

Features

  • Compliant with ISO 26262 (ASIL-B) functionality safety standard for automotive
  • System-on-chip (SoC) for automotive that enables the highest level of performance
  • Availability of SIP modules with external memory to reduce the design workload
  • Compatibility with previous products enables use of existing ecosystem and access to over 180 R-Car Consortium partners

Applications

  • In-vehicle infotainment systems
  • Driving safety support systems

Documentation & Downloads

Title Other Languages Type Format File Size Date
Other
R-Car H3 / M3 User's Manual – Other PDF 13.71 MB
info: For device-specific or order-specific documentation, submit a support request.

Boards & Kits

Part Number Title Type Company
R-Car-H3-M3-Starter-Kit R-Car H3 and M3 Starter Kit Starter Renesas

News & Additional Resources

Type Date
R-Car H3/M3 (Cockpit) Forum (for R-Car H3 and M3 Starter Kit) External Link Sep 1, 2020
R-Car/Boards/Yocto-Gen3-CommonFAQ on elinux.org (for R-Car H3 and M3 Starter Kit) External Link Aug 29, 2020
R-Car Consortium Page Jul 15, 2020
R-Car H3/M3/H2/M2/E2 Software Library and Technical Documents Page Jul 15, 2020
Automotive Software & Tools Page May 5, 2020

Specification

Item R-Car H3 Specifications
Product Name
(Part Number)		 R-Car H3 (R8J77950 (SiP), R8A77950 (SoC))
Power Supply Voltage 3.3V/1.8V (IO), 1.1V (LPDDR4), 0.8V (core), 2.5V (Ethernet AVB)
CPU Core Arm® Cortex®-A57
Quad		 Arm® Cortex®-A53
Quad		 Arm® Cortex®-R7
Dual lockstep
Cache Memory L1 instruction cache: 48KB
L1 operand cache: 32KB
L2 cache: 2MB		 L1 instruction cache: 32KB
L1 operand cache: 32KB
L2 cache: 512KB		 L1 instruction cache: 32KB
L1 operand cache: 32KB
External Memory LPDDR4-SDRAM
Maximum operating frequency: 1600MHz
Data bus width: 32 bits x 4 ch (12.8GB/s x 4)
Expansion Bus PCI Express 2.0 (1 lane) x 2 ch
3D Graphics IMG PowerVR Series6XT GX6650
Video Display Out x 3 ch
Video Input x 8 ch
Video codec module (H.265, H.264/AVC, MPEG-4, VC-1, etc.)
IP conversion module
TS Interface x 2 ch
Stream and Security Processor
Video image processing (up and down scaling, dynamic γ correction, color space conversion, I/P conversion, super resolution processing, rotation, visual near lossless image compression)
Distortion compensation module x 4 ch (IMR-LSX4)
High performance real-time image recognition processor (IMP-X5)
Audio Audio DSP
Sampling rate converter × 10 ch
Serial sound interface × 10 ch
MOST DTCP
Storage Interfaces USB 3.0 host interface (DRD) × 1 ports (wPHY)
USB 2.0 host/function/OTG interface × 4 ports (wPHY)
SD host interface × 4 ch (SDR104)
Multimedia card interface × 2 ch
Serial ATA interface × 1 ch
In-car Network and
Automotive Peripherals		 Media Local Bus (MLB) interface × 1 ch (3-pin interface)
Controller Area Network (CAN-FD support) interface × 2ch
Ethernet AVB 1.0-compatible MAC built in
Interface: RGMII
Ethernet AVB (802.1BA)
  • IEEE802.1BA
  • IEEE802.1AS
  • IEEE802.1Qav
  • IEEE1722
Security Crypto engine (AES, DES, Hash, RSA) × 2 ch
System RAM
Other Peripherals SYS-DMAC x 48 ch, real-time-DMAC x 16 ch
Audio-DMAC x 32 ch, audio (peripheral)-DMAC x 29 ch
32-bit timer x 26 ch
PWM timer × 7 ch
I2C bus interface × 7 ch
Serial communication interface (SCIF) × 11 ch
Quad serial peripheral interface (QSPI) x 2 ch (for boot, HyperFlash support)
Clock-synchronized serial interface (MSIOF) × 4 ch (SPI/IIS)
Ethernet controller (IEEE802.3u, RMII, without PHY)
Digital radio interface (DRIF) × 4 ch
Interrupt controller (INTC)
Clock generator (CPG) with built-in PLL
On-chip debugger interface
Low Power Mode Dynamic power shutdown
AVS (Adaptive Voltage Scaling), DVFS (Dynamic Voltage and Frequency Scaling), DDR-SDRAM power supply backup mode
Package 1255-pin SiP module (42.5mm × 42.5mm, 1.0mm pitch)
1384-pin Flip chip BGA (21mm × 21mm, 0.5mm pitch)
Development
Environment		 ICE for Arm CPU available from different vendors
Evaluation Board A user system development reference platform offering the following features is also available, enabling the users to carry out efficient system development.
(1) Includes car information system-oriented peripheral circuits, providing users with an actual device verification environment.
(2) Can be used as a software development tool for application software, etc.
(3) Allows easy implementation of custom user functions.
Software Platform Supported operating systems: Linux, Android, QNX® Neutrino® RTOS, Green Hills INTEGRITY® RTOS and Multivisor™, others
OpenGL ES3.1 3D graphics library, wide variety of H.265, H.264, MPEG-4 and VC-1 for video compliant with OpenMAX IL I/F in addition to BSPs compliant with OSs standard API are available to realize complete system concept.

(Remarks)
Arm, Cortex is a registered trademark of Arm Limited. NEON is a trademark of Arm Limited.
PowerVR, SGX is a trademark or a registered trademark of Imagination Technologies Ltd. (UK).v
CAN (Controller Area Network): An automotive network specification developed by Robert Bosch GmbH of Germany.
Linux is a registered trademark or trademark of Linus Torvalds in Japan and other countries.
QNX and Neutrino are trademarks of QNX Software Systems GmbH & Co. KG, registered in certain jurisdictions, and are used under license by QNX Software Systems Co.
Other product names and service names mentioned are the trademarks or registered trademarks that all belong to each owner.