The RF buffer portfolio features devices with very low noise floor characteristics and a negligible additive phase noise. Connected to Renesas synchronizers and JESD204B/C clock jitter attenuators, the devices extend the output signal fanout without compromising AC performance. The low-skew outputs keep the distributed signals phase aligned. Single and dual-channel architectures are available for the distribution of clock and synchronization signals in JESD204B/C systems. The devices support a differential I/O architecture and frequencies in the high-MHz and GHz range. Additional flexibility is provided by configurable phase delay, output format and amplitude control, phase alignment across multiple devices. Integrated frequency dividers scale a high input frequency to a lower output frequency.

Download: RF Timing Family Product Overview (PDF)

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