The 8V44N4614 is a FemtoClock® NG Clock Generator. The device has been designed for frequency generation in high-performance systems such wireless base-band boards, for instance to drive the reference clock inputs of processors, PHY, switch and SerDes devices. The device is very flexible in frequency programming. It allows to generate the clock frequencies of 156.25MHz, 125MHz, 100MHz and 25MHz individually at three output banks. One output bank supports configurable LVDS, LVPECL, the other two output banks support LVCMOS output levels. All outputs are synchronized on the incident rising edge, regardless of the selected output frequency. Selective single-ended LVCMOS outputs can be configured to invert the output phase, effectively forming differential LVCMOS output pairs for noise reduction. The PLL reference signal is either a 25MHz, 50MHz, 100MHz or 200MHz differential or single-ended clock.
The device is optimized to deliver excellent period and cycle-to-cycle jitter performance, combined with good phase noise performance, and high power supply noise rejection.

The device is configured through an SPI serial interface. Outputs can be configured to any of the available output frequencies. Two hardware pins are available for selecting pre-set output enable/disable configurations. In each of these pre-set configurations, each output can be enabled/disabled individually. A separate test mode is available for an increase or decrease of the output frequencies in 19.53125ppm steps independent on the input frequency. The device is packaged in a lead-free (RoHS 6) 48-lead VFQFN package. The extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements.


  • Clock generator for wireless base-band systems
  • Drives reference clock inputs of processors, PHY, switch and
    SerDes devices
  • FemtoClock® NG technology
  • Three low-skew, differential LVDS, LVPECL configurable clock
  • Ten low-skew, LVCMOS/LVTTL clock outputs
  • Input: 200MHz, 100MHz, 50MHz, 25MHz single-ended  
    (LVCMOS) or differential reference clock (LVDS, LVPECL)
  • Output clocks support 156.25MHz, 125MHz, 100MHz and 25MHz
  • Individual output disable (high-impedance)
  • Two sets of output enable configurations
  • PLL lock detect output
  • Test mode with frequency margining with 19.53125ppm steps
    (range ±507.8125ppm)
  • LVCMOS (1.8V, JESD8-7A) compatible SPI programming
  • Cycle-to-cycle jitter: 10ps (typical)
  • RMS period jitter: 1.6ps (typical)
  • Phase noise (12kHz - 20MHz): 0.40ps (typical)
  • 3.3V core and output supply
  • -40°C to +85°C ambient operating temperature
  • Lead-free (RoHS 6) 48-lead VFQFN packaging

Product Options

Part Number Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Active VFQFPN 48 I Yes Tray
Active VFQFPN 48 I Yes Reel
Active VFQFPN 48 I Yes Reel

Documentation & Downloads

Title language Type Format File Size Date
Datasheets & Errata
8V44N4614 Datasheet Datasheet PDF 835 KB
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-831 The Crystal Load curve Application Note PDF 395 KB
AN-846 Termination - LVDS Application Note PDF 133 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 115 KB
AN-839 RMS Phase Jitter Application Note PDF 233 KB
AN-832 Timing Budget and Accuracy Application Note PDF 131 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-837 Overdriving the Crystal Interface Application Note PDF 133 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-830 Quartz Crystal Drive Level Application Note PDF 143 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 136 KB
AN-801 Crystal-High Drive Level Application Note PDF 202 KB
AN-806 Power Supply Noise Rejection Application Note PDF 438 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
AN-803 Crystal Timing Budget and Accuracy for Renesas Timing Clock Products Application Note PDF 108 KB
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility Product Change Notice PDF 983 KB
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location Product Change Notice PDF 583 KB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB