The IDT 8P34S1208i is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8P34S1208i is characterized to operate from a 1.8V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8P34S1208i ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and eight low skew
outputs are available. The integrated bias voltage reference enables easy interfacing of AC-coupled signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.

特長

  • Eight low skew, low additive jitter LVDS output pairs
  • Two selectable, differential clock input pairs
  • Differential PCLK, nPCLK pairs can accept the following differential input levels: LVDS, LVPECL, CML
  • Maximum input clock frequency: 1.2GHz (maximum)
  • LVCMOS/LVTTL interface levels for the control input select pin
  • Output skew: 20ps (typical)
  • Propagation delay: 315ps (typical)
  • Low additive phase jitter, RMS
  • fREF = 156.25MHz, VPP = 1V, 12kHz - 20MHz: 41fs (typical)
  • Full 1.8V supply voltage
  • Lead-free (RoHS 6), 28-Lead VFQFN packaging
  • -40°C to 85°C ambient operating temperature

製品選択

製品名 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
8P34S1208NBGI
Active VFQFPN 28 I はい Tray
Availability
8P34S1208NBGI8
Active VFQFPN 28 I はい Reel
Availability

ドキュメント&ダウンロード

タイトル 他の言語 分類 形式 サイズ 日付
データシート
8P34S1208I Datasheet データシート PDF 940 KB
アプリケーションノート、ホワイトペーパー
AN-828 Termination - LVPECL アプリケーションノート PDF 322 KB
AN-846 Termination - LVDS アプリケーションノート PDF 133 KB
AN-844 Termination - AC Coupling Clock Receivers アプリケーションノート PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection アプリケーションノート PDF 495 KB
AN-840 Jitter Specifications for Timing Signals アプリケーションノート PDF 442 KB
AN-834 Hot-Swap Recommendations アプリケーションノート PDF 153 KB
AN-833 Differential Input Self Oscillation Prevention アプリケーションノート PDF 180 KB
AN-836 Differential Input to Accept Single-ended Levels アプリケーションノート PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced アプリケーションノート PDF 160 KB
AN-827 Application Relevance of Clock Jitter アプリケーションノート PDF 1.15 MB
AN-815 Understanding Jitter Units アプリケーションノート PDF 565 KB
AN-805 Recommended Ferrite Beads アプリケーションノート PDF 121 KB
PCN / PDN
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility 製品変更通知 PDF 983 KB
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location 製品変更通知 PDF 583 KB
その他資料
RF Timing Family Product Overview 概要 PDF 331 KB
IDT Clock Distribution Overview (Japanese) English 概要 PDF 7.79 MB
IDT Clock Generation Overview (Japanese) English 概要 PDF 2.19 MB